1. Field
Embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a nonvolatile memory device and a method for fabricating the same.
2. Description of the Related Art
A life environment is being changed such that anyone can conveniently use desired information anytime and anywhere, thanks to recently developed digital media devices. As a conversion is made from analog to digital, a variety of rapidly spreading digital devices require storage media capable of conveniently storing captured images, recorded music and various data. In order to meet this requirement, there is a growing interest in the field of a system-on-chip (SoC) according to a tendency for a high degree of integration of non-memory semiconductors, and semiconductor manufacturers compete to invest in the SoC field in an effort to strengthen SoC-based technology. In an SoC, multiple system technologies are integrated in one semiconductor.
In the SoC field where complicated technologies are integrated, a need for an embedded memory to trim an analog device or store an internal operation algorithm is gradually increasing as chips with a composite function in which a digital circuit and an analog circuit are mixed become more common. In particular, an embedded memory of interest is a flash electrically erasable programmable read-only memory (EEPROM). This is because the flash EEPROM is a highly integrated nonvolatile memory device which can store data even in a power-off state like a ROM and is capable of electrically erasing and programming data. EEPROMs include a single gate EEPROM which has one gate (for example, a floating gate), a stack gate (ETOX) EEPROM in which two gates (for example, a floating gate and a control gate) are vertically stacked, a dual gate EEPROM, and a split gate EEPROM.
Because the characteristics of an analog device can be affected by variation corresponding to the number of processes used to create the device, an embedded memory to be applied to a system-on-chip including an analog device should be fabricated using a CMOS process or a logic process while minimizing additional processes so that process variation is minimized.
However, in the conventional art, since the stack gate EEPROM, the dual gate EEPROM and the split gate EEPROM need additional processes to create additional structures, limitations exist in applying the stack gate EEPROM, the dual gate EEPROM and the split gate EEPROM to an embedded memory. Conversely, while the single gate EEPROM may be formed with fewer process steps, since a floating gate is coupled using a well which is formed in a substrate, the degree of integration of a single gate EEPROM is limited.
Accordingly, there is a need for a nonvolatile memory device capable of being fabricated in conformity with a logic process similar to a single gate EEPROM without increasing the degree of integration.